1. Field of the Invention
The present invention relates to a complementary type MOS field-effect transistor circuit (hereinafter, referred to as a C-MOS circuit) in which a P-channel MOS field-effect transistor (hereinafter, referred to as a P-MOST) and an N-channel MOS field-effect transistor (hereinafter, referred to as an N-MOST) are connected in series, and more particularly to an improvement of a gate protection structure to be applied to the C-MOS circuit.
2. Description of the Prior Art
An insulated gate field effect transistor has a gate electrode formed upon a thin gate insulator film. The gate insulator film is delicate to an electrostatic voltage and a high voltage noise applied to the gate electrode which cause a dielectric breakdown. In order to protect the gate insulator film from the dielectric breakdown, a protection circuit consisting of a resistor and a diode was heretofore inserted between an input terminal and the gate electrode.
A protection circuit was similarly required in a C-MOS circuit. Such protection circuit in the prior art was a circuit of a resistor and a diode inserted between an input terminal and a connection point of gate electrodes of P-MOST and N-MOST, as disclosed in U.S. Pat. No. 3,673,428 granted for Terry G. Athanas.
More specifically, a P-MOST, a P-well region, a P-type resistor region and a P-type diode region were formed in an N-type silicon substrate. An N-MOST and an N-type diode region were formed in the P-well region. The source-drain paths of the P-MOST and N-MOST were connected in series. The gate electrodes were commonly connected to each other. Thus, a C-MOS circuit was formed. Further, the commonly connected gate electrodes were connected to the P-type and N-type diode regions and to one end of the P-type resistor region. The other end of the P-type resistor region was in turn connected to an input terminal. A protection circuit was thus formed by the P-type and N-type diode regions and the P-type resistor region. Due to such protection circuit, the voltage applied to the gate electrodes of the P-MOST and the N-MOST was limited below the breakdown voltages of the diodes of the P- and N-type diode regions, when a high positive or negative voltage was applied to the input terminal.
The diodes in the protection circuit were reverse biased at a period when an input signal was normal. Under such condition, the reverse biased diodes operate as capacitors due to their junction capacitances. Therefore, the CR time constant of the protection circuit was large. The protection circuit deteriorated the high frequency characteristics of the C-MOS circuit. Furthermore, the protection circuit itself was destroyed by high voltage. There were two measures for enhancing the duration of the protection circuit. One was to enlarge the PN junction areas of the diodes and another was to enlarge the resistance of the resistor. Both measures resulted in further increment of the CR time constant and in additional decrement of high frequency characteristics.